Typically, in semiconductor chip applications, in a field effect transistor (FET), such as a junction gate field-effect transistor (JFET) there is a relationship between the pinchoff voltage Vp (the gate voltage at which the device will no longer conduct between the source and drain) and the on resistance Ron (the linear relationship between drain to source voltage and drain current for low drain to source voltage). The relationship is that current methods of reducing Ron have the effect of increasing Vp. Therefore it is difficult to fabricate a JFET device with a low Vp (ie within the Vdd range of a given technology) while maintaining a low Ron.